1. Field of the Invention
The present invention relates to a semiconductor circuit device, and more specifically to a semiconductor circuit device suitable for use as a ratio circuit (level shift circuit) composed of CMOS circuits to transmit signals from small potential difference logic circuits to large potential difference logic circuits in an integrated circuit.
2. Related Art
Conventionally, in a ratio circuit used in a CMOS integrated circuit, the output level of the ratio circuit is generally controlled on the basis of a change in the small input level, by use of a constant current generating circuit and a transistor switched on the basis of change of the input signal level.
FIG. 6 is a circuit diagram showing a known semiconductor circuit device.
As shown in FIG. 6, the ratio circuit is composed of a bias circuit block 5 and an output circuit block 6 connected in series to each other.
The bias circuit block 5 has a CMOS structure obtained by connecting a P-channel transistor 1 and an N-channel transistor 2 in series to each other, in which two drains of the two transistors 1 and 2 are connected in common and derived to a node 9.
Further, a voltage VDD is supplied from a high potential power source 7 to a source of the transistor 1.
Also, the gate of the transistor 2 is connected to a drain thereof, and a voltage GND of a low potential power source 8 is connected to a source of the transistor 2.
An input bias INBIAS is applied to a bias input terminal 11.
The output circuit block 6 has a CMOS structure obtained by connecting a P-channel transistor 3 and an N-channel transistor 4 in series to each other, in which two drains of the two transistors 3 and 4 are connected in common as an output terminal 12 and derived to an output terminal 12.
Further, the voltage VDD is supplied from the high potential power source 7 to a source of the transistor 3, and an input terminal 10 is connected to a gate of the same transistor 3.
Also a voltage GND of the low potential power source 8 is connected to a source of the transistor 4, and the node 9 derived from the common-connected drains of the two transistors 1 and 2 is connected to a gate of the transistor 4.
Further, an input signal IN is applied to the input terminal 10, and an output signal OUT is outputted from the output terminal 12.
In the circuit described above, when the threshold voltages of the transistor 1 is denoted by VthP1, a voltage V1 which satisfies the following relationship EQU VDD-VthP1&gt;V1 (1)
is always applied as the input bias signal INBIAS. As a result, the bias current IB1 flows through the transistor 1. Thus, transistor 2 is saturated and thereby kept turned on at all times. The voltage VBIAS11 at the node 9 can be determined based on the resistance ratio between the transistor 1 and the transistor 2. As a result, it is possible to always keep the voltage VBIAS1 at a constant voltage.
Although the voltage VBIAS1 applied from the node 9 is supplied to the gate of the transistor 4 of the output circuit block 6, since this voltage is kept constant, the turn-on resistance of the transistor 4 is constant.
Further, when the input signal IN is applied to the input terminal 10, the change range of the input signal voltage VIN is determined as EQU VDD.gtoreq.VIN.gtoreq.V1 (2)
As a result, when the input signal voltage VIN is the voltage V1, since the transistor 3 is turned on, output current IO1 flows from VDD, so that the output signal OUT of the output terminal 12 is at the voltage VDD. On the other hand, when the input signal voltage IN is at the voltage VDD, since the transistor 3 is turned off, the output signal OUT of the output terminal 12 is at the grounded voltage GND via the transistor 4. That is, since the voltage VBIAS11 at the node 9 is kept constant, transistor 2 can function as a constant current source.
FIG. 7 is an input/output waveform diagram for explaining the operation of the above-mentioned operation, in which (A) represents the waveform of the input signal VIN, (B) represents the waveform of the voltage VBIAS1, and (C) represents the waveform of the output signal OUT, respectively.
In the semiconductor circuit device described above, referring to the output waveforms shown in FIG. 7(C), a fall delay time from VDD to GND is longer than a rise delay time from GND to VDD. In other words, since the transistor 4 of the output circuit block 6 is always turned on, when VDD is outputted, the current capability of the transistor 4 exceeds that of the transistor 3 because the transistor 3 is turned on, so that the output signal OUT can reach the voltage VDD at a high speed. In contrast, when the output signal OUT falls, since the transistor 3 is turned off, a load capacitance on the side of the output terminal 12 is discharged through the transistor 4 having a relatively large turn-on resistance, so that the delay time of the output signal OUT to GND increases.
In summary, in the known semiconductor circuit device, the circuit delay time is relatively long.
In addition, FIG. 8 shows the current consumptions of both the bias circuit block 5 and the output circuit block 6, in which (A) represents the bias current IB1 supplied from VDD and (B) represents the output current IO1 flowing through the transistor 3.
As shown in FIG. 8, in the bias circuit block 5, since both transistors 1 and 2 are turned on, the bias current IB1 is always kept constant, irrespective of the input signal IN. In contrast, since the voltage VBIAS1 at the node 9 is always kept constant, transistor 4 is kept turned on at all times so as to function as a constant current source, so that the current flowing therethrough is constant. In contrast, transistor 3 is turned on or off according to the input signal IN. That is, when the input signal IN is at the voltage VDD, since the transistor 3 is turned off, no through current flows through the output circuit block 6. However, when the input signal IN is at the voltage V1, since the transistor 3 is turned on, the output current IO1 flows through the output circuit block 6.
In summary, in the prior art semiconductor circuit device, the power consumption is undesirably large due to the through current flowing through the transistors 3.